1. Field of the Invention
This invention relates in general to integrated circuits and, more particularly, to devices and methods for controlling biasing current of input buffers of integrated circuits over variations, such as voltage, temperature and process variations.
2. State of the Art
The first element of any integrated circuit data path is a data input buffer. Input buffers may be implemented in semiconductor devices using, for example, CMOS transistors which may be arranged generally in the form of cascaded inverters. Such transistors are sized to carefully provide high speed operations as well as to provide specific transition points resulting in the assignment of an input signal to either of a high or low logic output state. Designing an input buffer to meet various specifications generally requires a flexible design due to the variations in temperature, supply voltage and process variations. Because of such variations, the performance of an input buffer is often not determined by simulation but rather by the fabrication of an actual design.
Various input buffer designs for buffering an input signal prior to coupling that signal to other circuitry are well known in the prior art. Because of variations in, for example, power supply signal levels, a basic inverter-based input buffer may not meet specific design goals, an example of which is the centering of a trip-point or signal level at which an input signal will be designated as being of one of two logic levels. To specify a specific trip-point at which an input buffer characterizes an input signal as being of one of two signal levels, differential input buffers have been designed. FIG. 1 illustrates a simplified CMOS differential amplifier configured as an input buffer 10. Such a configuration with an inverter output generates a valid CMOS logic level. Common-mode noise on the differential amplifier inputs is, ideally, rejected while amplifying the difference between the input signal and the reference signal. The differential amplifier input common-mode range, for example a few hundred mV, sets a minimum input signal amplitude centered around VREF which causes the output signal, OUT, to change states. The speed of the configuration of input buffer 10 of FIG. 1 is limited by the differential amplifier biasing current. Generally, a large current increases the input receiver speed and decreases the amplifier gain, thereby reducing the differential amplifier's input common mode range. One shortcoming of the input buffer 10 is that it requires an additional external biasing circuit to generate the bias signal.
FIG. 2 illustrates an input buffer 20 arranged in a self-biasing configuration which does not need an additional circuit for generating a bias signal. Input buffer 20 is configured by joining a p-channel differential amplifier and an n-channel differential amplifier at the active load terminals. In input buffer 20, an adjustable biasing configuration is arranged which is potentially very efficient and fast at switching the input signal level to a valid output logic level. Self-biasing buffers and amplifiers are frequently utilized because of their simple architecture and fast switching speeds. However, as previously stated, the biasing current is very sensitive to power supply voltage, temperature and process variations. In one example (see FIG. 3), the biasing current may vary from 88 μA to 304 μA for each input buffer. For a device, such as a memory device which includes 16 or more input buffers, the total biasing current may vary widely, for example from between 3.5 mA to 12.5 mA, or over 300%, in the case of a DDR2 DRAM using 43 input buffers.
As an illustrative example, FIG. 3 illustrates a plot of input buffer biasing current variations over varying conditions for a conventional DDR2 (dual data rate) input buffer for a DRAM. FIG. 3 illustrates a graph 30 depicting variations in supply voltage with plots 32 and 34 and the plots are also a function of process and temperature variations 36–50. Each of the variations 36–50 illustrates process variations “FST” where “F” and “S” represent the speed nature (e.g., “F” for fast and “S” for slow) for the respective n-channel and p-channel devices when subjected to corresponding process variations. “T” represents temperature variations of the input buffer. As illustrated, the input buffer biasing current varies dramatically between process variations which include slow n-channel and p-channel devices at 110° C. with low supply voltage and variations which include fast n-channel and p-channel devices at −40° C. with high supply voltage. Therefore, there is a need for an improved input buffer circuit biasing arrangement which minimizes excessive biasing current over the various variation conditions.